Developer CD Series 1999 November: Tool Chest/Dev.CD Nov 99 TC.toast/Tool Chest/Testing & Debugging/Performance tools/4PM 4.6/4PMv4.6/4PMv4.6.rsrc/STR#_26724.txt

Text File | 1999-04-22 | 8.2 KB | 641 lines

Minimum time between last End of Data (EOD) to next request (TA)

Minimum number of consecutive Transactions that also meet the latency requirment between these transactions

Burstiness Counts the number of times there are at least X Transactions in a row with an acceptable Latency of Y cycles between any two Transactions

PCI Read from memory commands (read, read line, read multiple)

Processor waits on PCI transaction

L2 castout  waits for L2 castout buffer

Delay between Bus Request 1 to qualified Bus Grant 1

Delay between Bus Request 0 to  qualified Bus Grant 0

TA Overlap

Counter increments when Threshold is exceeded

•rbt• Total forced pages closed

•rbt• Total hits Pg0 & Pg1

•rbt• Total misses Pg0 & Pg1

•rbt• Force Pg1 closed: excl refresh

•rbt• Force Pg0 closed: excl refresh

•rbt• Pg1 Rd/Wrt hit: not piped

•rbt• Pg1 Rd hit: not piped

•rbt• Pg1 Rd/Wrt hit: piped

•rbt• Pg1 Rd hit: piped

•rbt• Pg0 Rd/Wrt hit: not piped

•rbt• Pg0 Rd hit: not piped

•rbt• Pg0 Rd/Wrt hit: piped

•rbt• Pg0 Rd hit: piped

•rbt• Pg1 Rd/Wrt miss: not piped

•rbt• Pg1 Rd miss: not piped

•rbt• Pg1 Rd/Wrt miss: piped

•rbt• Pg1 Rd miss: piped

•rbt• Pg0 Rd/Wrt miss: not piped

•rbt• Pg0 Rd miss: not piped

•rbt• Pg0 Rd/Wrt miss: piped

•rbt• Pg0 Rd miss: piped

SDRAM pages are disabled this is probably worthless

•stt• PCI Reads that hit ...

•rbt• PCI trans. that disconnect at end of Cache line

•rbt• PCI Rd/Wrt hit mod. in CPU Cache

•rbt• PCI Rd hit mod. in CPU Cahce

•rbt• PCI Read Buffer

•rbt• PCI Rd Buf while Spec. fetch

•rbt• PCI Rd Buf filling after disconnect

•rbt• pin TRDY is asserted

•rbt• pin IRDY is asserted

•rbt• pin FRAME is asserted

•rbt• Read, Spec. & Write snoops

•rbt• Read & Speculative snoops

•rbt• Speculative Snoops

•rbt• PCI Wrt w inval. to Memory Cmd

•rbt• PCI Reads from ROM

•rbt• PCI Read mult. from Memory Cmd

•rbt• PCI Read line from Memory Cmd

•rbt• Beats data Rd/Wrt Ext. PCI Master

•rbt• Beats data Read Ext. PCI Master

•rbt• PCI Read/Write Memory Cmd

•rbt• PCI Cycles

Because this is PCI based counts are in PCI Cycles *not* CPU cycles

•rbt• Memory busy: Reads/Writes

Number of bus cycles waiting to Read from RAM

Number of bus cycles waiting to Read from ROM

•rbt• Retries of Grackle on 60x bus

Number of cycles Alternate Master retries on 60x bus

Number of cycles Grackle retries 60x bus

Number of cycles the Data Busy (all data transfers)

Number of cycles the Address Bus is Busy (all phases)

•rbt• Addr. ONLY trans, NOT retried

•rbt• Sync/Eieio trans NOT retried

•rbt• Total L2 castouts

•rbt• L2 castouts, no retry

•rbt• Cache-inhibited trans, NOT retried

Number of Bus Cycles, compare to CPU cycles to get CPU to Bus ratio

Because this is Grackle based counts are in Bus Cycles *not* CPU cycles

Count Read transactions

Count Write transactions

Grackle can have its own attached L2, a G3's backside L2 is *NOT* grackle attache so this is normally 0

events targeted at memory

events targeted at PCI

The OS does write to the ROM 'cause its safe so don't be suprised

Burst transactions take four cycles

Single Beat transactions take one Bus cycle

revert to what was previously set

use the current settings

•stt• Select Periodic Interval

•rbt• Other...

•rbt• 1 second

•rbt• 100 milliseconds

•rbt• 10 milliseconds

•stt• No Data taken this run

•stt• Name taken.  Please choose another name

•stt• (1 to 10,000 milliseconds)

•stt• Enter Sample Rate

•stt• Save changes to before closing?

•icn•

•btn• Don't Save

•btn• Save

•stt• Enter Repeat Value (1 - 32):

•stt• Enter Threshold Value (0 - 63):

•btn• Cancel

•stt• of

•utm•

•stt• PM604 v0.0 results for run #

•stt•

•btn• OK

Memory Events are events in the Main Memory (not ROM)  domain

Burstiness

Configure PM0 to count Burstiness

Threshold Events are events that require a certain threshold to be exceeded before counting begins

PCI Events are events occurring in the PCI domain

Processor Events are events that are caused by or directed to the processor from Grackle

Processor  Transactions are Single Beat, Burst, Read, Write transacations from the processor to Memory, ROM, or PCI

Configure Grackle's counter 3 (AKA PM3)

Configure Grackle's counter 2 (AKA PM2)

Configure Grackle's counter 0 AND counter 1 to count Burstiness

Configure Grackle's counter 1 (AKA PM1)

Configure Grackle's counter 0 (AKA PM0)

spec br. fetch stall

fixed point

snoop retry

sync

success stwx

priv mk/nomk switch

mispredict branch

DTLB table walk cycles

L2 castouts

lr/ctr  depency stall

resolve br. 2nd spec

L1 load miss cycles

????

L2 cacheops

snoop castouts

floating point

stwx

user mk/nomk switch

taken branch

L2 data cache miss

DTLB miss

L1 data cache miss

resolve br. 1st spec

L1 icache miss cycles

sys unit inst.

L1 castout to L2

L1 and L2 snoops

loads and stores

reserved loads

pr. to user switch

Fall thru branch

L2 inst. cache miss

ITLB miss

L1 inst. cache miss

spec. br. dispatch stall

Unresoved branch

Load Waits

inst. bkpt match

inst. Fetch

L2 Hits

ITLB TW Cycles

No disp past br

XUnmod reads

STQ 3Entry cycles

STQ 1Entry cycles

hiPri snoop push

ARTRY

DBWO writes

Data bus pipe2

BG stall cycles

CRX stall cycles

SFX0 stall cycles

dTableWalk cycles

iTableWalk cycles

Disp interlock stall

Disp CRB stall

Disp GRB stall

Disp noUnit stall

Decode correction

4BB used

BATC hits

Load stall cycles

Inst to STQ

Unalign 2hits

L/S addr stall

L/S LDQ stall

L/S MMU stall

CR logical

Shared reads

STQ full retry

STQ 2entry cycles

Moveouts

WrtHitShr Kills

Fast L2 trans

Data bus pipe3

Data bus pipe1

NonCrit Fwds

SFX1 stall cycles

FP stall cycles

Data tableWalks

Inst tableWalks

Disp FPROB stall

Disp ROB stall

Disp inst stall

Disp correct

BU stall cycles

System calls

Inst stall cycles

ST stall cycles

Inst to LDQ

L/S no opnd stall

L/S STQ stall

L/S BIU stall

ST Queue entries

Unaligned stores

1Dispatch cycles

2Dispatch cycles

3Dispatch cycles

4Dispatch cycles

L2_INT hi cycles

FP idle cycles

SFX1 idle cycles

CFX idle cycles

Cycles EE off

Softstop Bkpts

LD Queue entries

Unaligned loads

L2_INT trans

L/S idle cycles

SFX0 idle cycles

BU idle cycles

Float

EIEIO

SYNC

Incorrect Branch

Data TLB miss

Icache Miss

Inst. dispatch

PMC2 Count Control

Count Disable

Enable

bit 47

bit 51

bit 55

bit 63

Show Addresses...

PCM2

PCM1

Overall

Delete

Describe

Intervals...

Launch Again

Repeats...

Launch...

The NMI switch is pre-empted for starting and stopping

Allows you to use the Grackle (MPC106) performance counters by enabling the Grackle menu

Snoop hits

CFX dispatch

Loads

SFX0 dispatch

Branch dispatch

CFX

SFX0

Branch Unit Result

ISYNC

ICBI

MFSPR

STCX

Branches

Inst TLB miss

Data cache miss

Load cycles

Inst dispatch

Instructions

Store miss (no L2)

Load miss (no L2)

Snoops (hit or miss)

Float dispatch

SFX1 dispatch

Ld/st dispatch

Number of Floating Point instructions completed

SFX1

Load/store

Float non ld/st

Fixed non ld/st

Number of EIEIO instructions

Number of SYNC instructions

MTSPR

Store miss (L2)

Load Miss (L2)

LARX

Number of Incorrect Branchs

Number of Data TLB misses

Number of Instruction cache misses

Instructions dispatch but not necessarily completed

TimeBase

Instructions completed

Cycles

NULL

All Not Marked is essentially evrything but the 68K emulator code

All Marked is essentially 68K emulator code in User State

For MacOS, 8.x at least, everything runs as unmarked

For MacOS, all code except 68K emulator running in User state

For MacOS this is essentially the time in the 68K emulator

Counts code that does not run in nanokernal

Counts Only in Supervisor state, i.e., nanokernal

Always counts regardless of the state: UnConditional

Time Base

604e/v PMC4

604e/v PMC3

604e/v PMC2

604e/v PMC1

Allows you to select the "state" of the machine in which to limit the counts, applys to all counters

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Now supporting MPC106 (AKA Grackle) Performance Counters